Ramesh Karri
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Professor
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Co-founder and co-chair NYU Center for Cybersecurity
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Founder and Organizer: Annual CSAW Embedded Security Challenge
Ramesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.
He has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).
He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS (cyber.nyu.edu), co-founded the Trust-Hub (trust-hub.org/) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, (www.nyu.edu/csaw2016/csaw-embedded).
He co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).
He was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).
Education
University of Hyderabad 1988
Master of Technology, Computer Science
Andhra University 1985
Bachelor of Engineering, Electronics and Communication Engineering
University of California, San Diego 1992
Master of Science, Computer Engineering
University of California, San Diego 1993
Doctor of Philosophy, Computer Science
Experience
Polytechnic Institute of New York University
Associate Professor
Research and teaching in computer engineering. Current research focus is on trustworthy and secure hardware.
From: September 1998 to August 2011
Fifth Generation Computing Group, CMC Research and Development Ce
Research Engineer
Implemented multiprocessor cache consistency protocols and evaluated their performance and scalability.
From: May 1988 to June 1989
University of California, San Diego
Graduate Teaching and Research Assistant
From: September 1989 to August 1993
University of Massachusetts, Amherst
Assistant Professor of Electrical and Computer Engineering
Research and teaching in computer engineering.
From: September 1993 to July 1998
Lucent Bell Labs Engineering Research Center, Princeton
Member of Technical Staff
On-line built-in self test of VLSICs
From: June 1997 to July 1998
New York University
Professor
Research and teaching in computer engineering. Current research focus is on trustworthy and secure hardware.
From: September 2011 to present
Research News
Tracking Real-time Anomalies in Power Systems (TRAPS)
The researchers participating in this grant include Farshad Khorrami and Ramesh Karri, Professors of Electrical and Computer Engineering and member and director — respectively — of the NYU Center for Cybersecurity; and Research Scientist Prashanth Krishnamurthy.
A project to develop methods of securing the U.S. power grid from hackers, led by NYU Tandon researchers at the NYU Center for Cybersecurity, is one of six university teams receiving a portion of $12 million from the U.S. Department of Energy (DOE), supporting research, development, and demonstration (RD&D) of novel cybersecurity technologies to help the U.S. power grid survive and recover quickly from cyberattacks.
The Tandon team received $1.94 million for the project from the DOE fund, with matching support from NYU bringing the total to around $2.8 million, to develop Tracking Real-time Anomalies in Power Systems (TRAPS) to detect and localize anomalies in power grid cyber-physical systems. Collaborators include SRI International, the New York Power Authority, and Consolidated Edison. TRAPS will correlate time series measurements from electrical signals, embedded computing devices, and network communications to detect anomalies using semantic mismatches between measurements, allowing it to perform cross-domain real-time integrity verification.
Administered by the DOE's Office of Cybersecurity, Energy Security, and Emergency Response (CESER), the strategic project aims to advance anomaly detection, artificial intelligence and machine learning, and physics-based analytics to strengthen the security of next-generation energy systems. These systems include components placed in substations to detect cyber intrusions more quickly and automatically block access to control functions.
The program aligns with the DOE’s larger goal of bolstering the security and resiliency of the power grid toward advancing President Biden’s goal of a 100% clean electrical grid by 2035 and net-zero carbon emissions by 2050.
Detection of Hardware Trojans Using Controlled Short-Term Aging
This research project is led by Department of Electrical and Computer Engineering Professors Farshad Khorrami and Ramesh Karri, who is co-founder and co-chair of the NYU Center for Cybersecurity, and Prashanth Krishnamurthy, a research scientist at NYU Tandon; and Jörg Henkel and Hussam Amrouch of the Computer Science Department of the Karlsruhe Institute of Technology (KIT), Karlsruhe, Germany.
The project builds upon on-going research, funded by a $1.3 million grant from the Office of Naval Research, to create algorithms for detecting Trojans — deliberate flaws inserted into chips during fabrication — based on the short term aging phenomena in transistors.
It will focus on this physical phenomenon of short-term aging as a route to detecting hardware Trojans. The efficacy of short-term aging-based hardware Trojan detection has been demonstrated through simulations on integrated circuits (ICs) with several types of hardware Trojans through stochastic perturbations injected into the simulation studies. This DURIP project seeks to demonstrate hardware Trojan detection in actual physical ICs.
Khorrami explained that the new $359,000 grant will support the design and fabrication of 28nm chips with and without built-in trojans
"The supply chain in manufacturing chips is complex and most foundries are overseas. Once a chip is fabricated and returned to the customer, the question is if additional hardware has been included on the chip die for most likely malicious purposes," he said.
For this purpose, this DURIP project is proposing a novel experimental testbed consisting of:
• A specifically designed IC that contains Trojan-free and Trojan-infected variants of multiple circuits (e.g., cryptographic accelerators and micrcontrollers). This IC will be used for evaluation of the efficacy and accuracy of the hardware short-term aging based Trojan detection methods. To validate the Trojan detection methodology the team will use 3mm×3mm ICs with both Trojan-free and Trojan-infected variants of multiple circuits.
• AnFPGA-based interface module to apply clock signal and inputs to the fabricated IC and collect outputs.
• A fast switching programmable power supply for precise application of supply voltage changes to the IC’s being tested. The unit will apply patterns of supply voltages to the test chips to induce controllable and repeatable levels of short-term aging.
• Finally, a data analysis software module on a host computer for machine learning based device evaluation and anomaly detection (i.e., detection of hardware Trojans).
This testbed, a vital resource in the physical validation of the proposed NYU-KIT hardware Trojan detection methodology will also be a valuable resource for evaluating and validating other hardware Trojan detection techniques developed by NYU and the hardware security researchers outside of NYU. The testbed will therefore be a unique experimental facility for the hardware security community by providing access to (i) physical ICs with Trojan- free and Trojan-infected variants of circuits ranging from moderate-sized cryptographic circuits to complex microprocessors plus (ii) a generic FPGA-based interface to interrogate and test these ICs for Trojans according to their detection method.
A survey of cybersecurity of digital manufacturing
This survey was led by Nikhil Gupta, professor mechanical and aerospace engineering and a member of the NYU Center for Cybersecurity; and Ramesh Karri, professor of electrical and computer engineering and co-founder and co-Chair of the NYU Center for Cybersecurity.
The Industry 4.0 concept promotes a digital manufacturing (DM) paradigm that can enhance quality and productivity, which reduces inventory and the lead time for delivering custom, batch-of-one products based on achieving convergence of additive, subtractive, and hybrid manufacturing machines, automation and robotic systems, sensors, com- puting, and communication networks, artificial intelligence, and big data. A DM system consists of embedded electronics, sensors, actuators, control software, and interconnectivity to enable the machines and the components within them to exchange data with other machines, components therein, the plant operators, the inventory managers, and customers.
Digitalization of manufacturing aided by advances in sensors, artificial intelligence, robotics, and networking technology is revolutionizing the traditional manufacturing industry by rethinking manufacturing as a service.
Concurrently, there is a shift in demand from high-volume manufacturing to batches-of-one, custom manufacturing of products. While the large manufacturing enterprises can reallocate resources and transform themselves to seize these opportunities, the medium-scale enterprises (MSEs) and small-scale enterprises with limited resources need to become federated and proactively deal with digitalization. Many MSEs essentially consist of general-purpose machines that give them the flexibility to execute a variety of process plans and workflows to create one-off products with complex shapes, textures, properties, and functionalities. One way the MSEs can stay relevant in the next-generation digital manufacturing (DM) environment is to become fully interconnected with other MSEs by using the digital thread and becoming part of a larger, cyber-manufacturing business network. This allows the MSEs to make their resources visible to the market and continue to serve as suppliers to OEMs and other parts of the manufacturing supply networks.
This article, whose authors include researchers from NYU Tandon and Texas A&M, explores the cybersecurity risks in the emerging DM context, assesses the impact on manufacturing, and identifies approaches to secure DM. It resents a hybrid-manufacturing cell, a building block of DM, and uses it to discuss vulnerabilities; discusses a taxonomy of threats for DM; explores attack case studies; surveys existing taxonomies in DM systems; and demonstrates how novel manufacturing-unique defenses can mitigate the attacks.
The team's research is supported, in part, by the National Science Foundation.